Altera 10-Gbps Ethernet IP

The Altera 10-Gbps Ethernet IP core implements the IEEE 802.3 2005 and 802.1Q Ethernet standards. Quartus II can be used to parameterize and implement the core in designs. The core includes an Ethernet Media Access Controller (MAC) with an Avalon Streaming (Avalon-ST) interface on the client side, and a XAUI or a standard XGMII interface on the network side. The XAUI interface is implemented as hard IP in an Altera FPGA transceiver or as soft logic, which results in a soft 10GBASE-X XAUI PCS. Alternatively, a 10-Gbps Ethernet IP core that includes only the MAC or the soft XAUI PCS can be implemented.

This core comes available automatically on PC Windows when installing Quartus from CMF.

This program is not readily available on central Linux services. However, if you wish to install the program on a local Linux machine, please contact eda.supprt@cern.ch for information on how to access the installation media.

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